This invention generally relates to semiconductor device manufacturing methods and more particularly to methods for forming a multi-layer protective coating including a plurality of protective sealing layers over low-k (dielectric constant) porous insulating material to prevent migration of chemical species including water (H2O).
Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been signal delay caused by parasitic capacitive effects of insulating materials in which metal interconnects are formed to interconnect devices. It has become necessary to reduce capacitance of the insulating layers to allow the insulating layer thicknesses to shrink along with other device features such as metal interconnect line width. As a result, the need for lower dielectric constant materials has resulted in the development of several different types of organic and inorganic low-k materials.
Manufacturing processes such as, for example, damascene processes, have been implemented to form metallization vias and interconnect lines (trench lines) by dispensing entirely with the metal etching process. The damascene process is a well known semiconductor fabrication method for forming multiple layers of metallization vias and interconnect lines (trench lines). For example, in the dual damascene process, a trench opening and via opening is etched in an insulating layer also known as an inter-metal or inter-level dielectric (IMD/ILD) layer. The insulating layer is typically formed over a substrate including another conductive area over which the vias and trench lines are formed and in communication with. After a series of photolithographic steps defining via openings and trench openings, via and the trench openings are filled with a metal, preferably copper, to form metallization vias and interconnect lines (trench lines), respectively. The excess metal above the trench line level is then removed by well known chemical-mechanical planarization (polishing) (CMP) processes.
As indicated, advances in semiconductor device processing technology demands the increasing use of low-k (low dielectric constant) insulating materials in, for example, IMD (ILD) layers that make up the bulk of a multilayer device. In order to reduce signal delays caused by parasitic effects related to the capacitance of insulating layers, for example, IMD layers, incorporation of low-k materials has become standard practice as semiconductor feature sizes have diminished. Many of the low-k materials are designed with a high degree of porosity to allow the achievement of lower dielectric constants. Several different organic and inorganic low-k materials have been developed and proposed for use in semiconductor devices as insulating material having dielectric constants less than about 3.0 for achieving integration of, for example, 0.13 micron interconnections. In the future, even lower dielectric constant material, for example less than about 2.5, will be required for 0.1 micron process integration, and dielectric constants of less than about 2.0 will be required for 0.07 micron process integration.
One exemplary low-k inorganic material that is frequently used, for example, is carbon doped silicon dioxide (C-oxide) formed by a CVD process where the dielectric constant may be varied over a range depending on the process conditions. C-oxide, for example, may be formed with dielectric constants over a range of about 2.0 to about 3.0 and density of about 1.3 g/cm3 compared to dielectric constants of about 4.1 and a density of about 2.3 g/cm3 for silicon dioxides (e.g., un-doped TEOS). Other exemplary low-k inorganic materials include porous oxides, xerogels, or SOG (spin-on glass). Exemplary low-k organic materials include polysilsequioxane, parylene, polyimide, benzocyclobutene and amorphous Teflon.
Low-k materials believed to be required to achieve integration of 0.07 micron devices will require low-k materials (ultra low-k) with a dielectric constant of less than about 2.0. Such low-k materials will typically require a porosity of 50 per cent to 80 percent by volume. An exemplary class of materials able to achieve this level of porosity includes porous silica films. Porous silica films are generally formed with a porosity of about 20% or greater and with pore sizes that range from about 1 nm to about 100 nm. The density of the silicon containing composition, including the pores, ranges from about 0.1 to about 1.9 g/cm3. Yet another material that has received recent attention for use as an ultra low-k material in semiconductor devices are mesoporous silicates, such as molecular sieve materials, that have a well determined pore structure with a narrow size distribution, such as a honeycomb structure including repeating units of cage-like pores. Examples of molecular sieves having, for example, a channel-typed micropore structure include TSM and silicalate. Mesoporous materials have a pore size from about 10 to about 500 Angstroms. These materials may have porosities from about 50 percent to about 80 percent and can have dielectric constants of less than about 2.0. One advantage of these materials is their relatively high strength due to their crystalline nature. Yet another class of ultra low-k materials includes aerogels. Aerogels are generally created by acid catalyzed hydrolysis of precursors such as tetraethylorthosilicate (TEOS) and tetramethylorthosilicate (TMOS) under controlled atmosphere conditions including and aging and drying period.
As might be expected, the development of porous low-k materials has presented several problems in manufacturing methods that must be overcome such as material strength and tendency to absorb chemical species such as water. One important limitation of porous low-k materials is low strength tendency to crack or peel in subsequent manufacturing processes including, for example, chemical mechanical planarization (CMP). In order to protect the porous low-k insulating material layers, it has been necessary to add a capping layer over the porous low-k insulating layer including for example, silicon nitride (SiN) and silicon oxynitride (SiON). Additionally, silicon carbide (SiC) has been used as a capping layer to protect the insulating layer in subsequent processing steps including CMP.
One problem with the prior art capping layer technology is that due to the high porosity present in low-k insulating materials, is that adhesion of the capping layers of the prior art is poor and undesirably add to the overall dielectric constant of the multi-layer device. For example, SiC has a dielectric constant of about 5.0 and the metal nitrides such as SiN and SiON have dielectric constants greater than 5.0. Capping layers are necessary, however, to protect the increasingly porous low-k materials have proven necessary to both protect the low-k material during subsequent processing steps including CMP, and to prevent the porous low-k material from absorbing moisture.
Many of the porous low-k and ultra low-k materials including mesoporous and nanoporous structures include an interconnecting pore structure that allows chemical species, such as water (H2O), to readily migrate through the low-k material presenting serious problems in subsequent processing steps. Thus, for example, during an RIE etching step in an oxygen containing plasma to remove the photoresist used to pattern via openings or trench openings, the low-k material produces hydrophilic bonds and absorbs moisture. During subsequent metal deposition to fill via holes and trench openings to form metal interconnects, outgassing of the moisture occurs, causing oxidation of metal contacts resulting in via poisoning, or high resistivity of the via interconnect due to the oxidized metal contacts or interconnects. A further problem with water absorption on hydrophilic surfaces, such as nanoporous or mesoporous silica material, is that the absorption of water tends to significantly increase the dielectric constant of the porous silica material due to the high internal surface area of the material and consequently the large amount of water that may be absorbed. For example, a porous material with a dielectric constant of less than about 2 and a porosity of about 50 to 80 percent by volume can absorb enough water to raise the dielectric constant to about 4.0.
Another problem with migrating chemical species in porous low-k materials, concerns amine and other nitrogen-containing hydrophilic species originating from, for example, metal nitride layer forming CVD processes that may readily diffuse into an underlying or overlying porous low-k insulating layer. The nitrogen containing species are believed to later diffuse out to interfere with a subsequent photolithographic exposure and development process using acid generated photoresists, such photoresist used, for example, in many deep ultraviolet (DUV) photolithographic patterning processes. The contaminating nitrogen-containing is believed to diffuse out of the low-k insulating layer during a subsequent photoresist process interfering with the photoresist development process thereby altering resist profiles by having undeveloped photoresist remain deposited on feature edges and sidewalls.
The prior art has attempted to solve this problem by employing several different types of chemical surface hydrophobic modifying agents designed to cap the exposed silanol (hydrophilic) species on the internal surface area of the porous material to prevent absorption and migration of hydrophilic species. One problem with this approach is that the surface modifying agents tend to decrease the porosity of the material and therefore raise the dielectric constant as they penetrate into the interconnecting pore structure of the material to react with exposed surface silanol species.
It would therefore be advantageous to develop a method for forming a protective layer over a low-k porous insulating material layer in a multiple layer semiconductor device that is able to preserve the porosity and therefore dielectric constant of the porous low-k material while sealing the porous material to the migration of chemical species, including water (H2O) into the low-k porous insulating material layer.
It is therefore an object of the invention to present a method for forming a protective layer over a low-k porous insulating material layer in a multiple layer semiconductor device that is able to preserve the porosity and therefore dielectric constant of the porous low-k material while sealing the porous material to the migration of chemical species, including water (H2O) into the low-k porous insulating material layer.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for forming a multi-layer protective coating over a porous low-k (dielectric constant) material for use in a multiple layer semiconductor device.
In a first embodiment, the method includes the steps of providing a semiconductor process wafer including providing a semiconductor process wafer including a process surface said process surface including an uppermost surface of a low-k porous material layer said low-k porous material layer including a plurality of openings penetrating the process surface to form a plurality of pore openings; and spin coating a flowable dielectric onto the process surface to form a plurality of protective layers such that the porosity of the low-k porous material layer is substantially maintained and the plurality of protective layers are formed such that migration of water (H2O) is substantially blocked through at least an uppermost protective layer surface.
In another embodiment, the step of spin coating further includes forming an initial protective layer over the process surface to at least partially cover the plurality of pore openings thereby forming a corresponding narrowed communication channel to include a closed communication channel disposed substantially over each pore opening of the plurality of pore openings to form a plurality of communication channels; forming at least one additional protective layer over the initial protective layer to at least narrow the plurality of communication channels to a diameter of less than about 5 Angstroms to include closing at least a portion of the plurality of communication channels.
In a related embodiment, the low-k porous material layer includes interconnecting pores having a pore diameter of from about 10 Angstroms to about 500 Angstroms. In other related embodiments, the low-k porous material layer has a dielectric constant of less than about 3.0. Further the low-k porous material layer has a dielectric constant of less than about 2.0.
In other embodiments, the low-k porous material layer includes at least one of a porous silica, a mesoporous silicate, an aerogel, or a xerogel. Further, the low-k porous material layer includes a mesoporous material with a dimensionally consistent pore structure. Further yet, the flowable dielectric forms a silicon oxide containing material. Yet further, the plurality of protective layers have a density of from about 2.2 to about 2.4 gms/cm3.
In yet another embodiment, the plurality of protective layers are impermeable to water. Further, the plurality of protective layers are formed having a total thickness of less than about 1000 Angstroms. In a related embodiment, the plurality of protective layers are formed having substantially the same thickness. Further, each protective layer of the plurality of protective layers is formed having a sequentially decreasing thickness from an initial protective layer thickness.
In another embodiment, the step of spin coating further includes dispensing a selectable amount of flowable dielectric onto the process wafer surface while spinning the process wafer to form a substantially uniform layer of the flowable dielectric; spin drying the substantially uniform layer of flowable dielectric by spinning the process wafer for a period of time sufficient to form an at least partially polymerized protective layer over the process wafer surface including at least a portion of the pore openings; repeating the dispensing and spin drying steps to form a plurality of the at least partially polymerized protective layers; baking the plurality of the at least partially polymerized protective layers at a temperature for a period of time; and, curing the plurality of the at least partially polymerized protective layers at a temperature for a period of time to form a plurality of substantially polymerized protective layers.
In related embodiments, the step of dispensing further comprises spinning the process wafer at a spin rate of from about 1000 to about 4000 rpm. Further, the step of spin drying further comprises spinning the process wafer at a spin rate of from about 2000 to about 4000 rpm. Further yet, the step of baking further comprises heating the process wafer at one or more temperatures ranging from about 50 to about 300 degrees Centigrade for a total heating period of from about 1 minute to about 10 minutes. Yet further, the step of curing further comprises heating the process wafer at one or more temperatures ranging from about 200 to about 500 degrees Centigrade for a total heating period of from about 5 minutes to about 20 minutes.
In another embodiment, at least one of the steps of dispensing, baking and curing are selectively carried out under controlled ambient conditions including a pressure.
In yet another embodiment, an outgassing step is performed to outgas moisture from the low-k porous material layer prior to forming a protective layer included in the plurality of protective layers such that water (H2O) is substantially blocked from migrating through the at least an uppermost protective sealing layer surface.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying FIGS.